Bachelor's/Master's in Electronics, Electrical Engineering.
5-9 years of experience in layout activities of complex SOC
Knowledge of tools like Synopsys ICC, Primetime STA, Power analysis tools like primerail
Layout and timing closure of digital macros and having worked on million gate design layout
Usage of Synopsys ICC tools
Knowledge of STA and having worked on large million gate layouts
Knowledge of ASIC design flow
Knowledge of low power design methodologies and high performance designs
Physical verification activities.
5-9 years of experience in layout activities of complex SOC
Knowledge of tools like Synopsys ICC, Primetime STA, Power analysis tools like primerail
Layout and timing closure of digital macros and having worked on million gate design layout
Usage of Synopsys ICC tools
Knowledge of STA and having worked on large million gate layouts
Knowledge of ASIC design flow
Knowledge of low power design methodologies and high performance designs
Physical verification activities.
To Apply and for detailed JDs:
Please send your profiles at artibhatia@embeddedcareers.com and or get registered at embeddedcareers.com.
Arti
Bhatia
Marketing Executive
Embedded Careers
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