Opening for Physical Design Engineer Experience 5-6years. To Apply and for detailed JDs: Please send your profiles at artibhatia@embeddedcareers.com and or get registered at embeddedcareers.com Location Colorado USA

SOC Encounter P&R, PrimeTime, Apache, Caliber
 Block builds that range in size from 100K to 1500K placed instances with flat hierarchy including embedded IP. Note this may also include padframe blocks.
o Individual engineer ownership to include 1-6 blocks depending on complexity (gate count, # clock domains, congestion, timing closure, etc….)
o Responsible for entire netlist to GDSII implementation for blocks. Includes floorplan for block (i.e. memory placement), P&R, DRC/LVS/ERC, PT-SI, Formal Verification, etc….
o Use flow which includes the following tools:
 Cadence: SOC-Encounter, GPS, Nano, Celtic, Conformal
 Synopsys: Physical Compiler, StarRC-XT, PT-SI
 Mentor: Calibre
  To Apply and for detailed JDs: Please send your profiles at artibhatia@embeddedcareers.com and or get registered at embeddedcareers.com.

Arti Bhatia                                                                    

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