To Apply and for detailed JDs:
Please send your profiles at artibhatia@embeddedcareers.com and or get registered at embeddedcareers.com.
For All Jobs:-: Product Domain Expertise: Semiconductor. Skill Category:
ASIC Design. Please apply only if physically present in US. H1 B, TN
Visa, can apply.
TEST
ENGINEER (Labview) Location: Oregon USA
Testing experience in products containing embedded
software.
Energy
meters, sub-meters experience
The ability to
read/understand C code.
7+ years of Test Engineer Experience.
Labview experience is
necessary
C++ PROGRAMMER Location:
South Carolina USA
C++ programming
Boost Library
STL
General windows programming
CLUSTER
SYSTEM TEST ENGINEERS Location: Michigan
Minimum 2-3 yrs of
experience in Cluster, Infotainment System level testing includes test cases
development based on product requirement and test execution.
QNX or Linux OS in terms of understanding the system log over
debug port ( RS232)
DGITAL
VERIFICATION ENGINEER Loc: California USA
- Minimum 7 years experience in
Ascii & system verification, processor verification, or Ed methodology
development.
- Strong knowledge of object
oriented hardware verification Languages such as System Verily or VERA, as well
as industry standard hardware design languages like Verily, VHDL, C & Lerp,
and System C.
DESIGN VERIFICATION ENGINEER Location: Pennsylvania
1) Block Verification -> System
Verilog-OVM skillset. 4 Positions
2) Multi Chip Verification ->
Specman- 6 Positions Specman
3) Modem Verification –> Modem IP
Verification- Specman- 2 Positions
USB VERIFICATION ENGINEER Location: California
• Knowledge of the USB3
protocol and signaling (level 1, level 2)
• Knowledge of the Synopsys USB3 macro
is preferred
• Knowledge of C/C++, System Verilog
FPGA EMULATION
ENGINEER Location: California
* 7 years experience working with emulation platforms
* Expert in FPGA synthesis, place, and route
* Familiar with Verilog RTL design and simulation
* Familiar Xilinx FPGA
* Familiar with schematic capture and circuit board design
* Expert in FPGA synthesis, place, and route
* Familiar with Verilog RTL design and simulation
* Familiar Xilinx FPGA
* Familiar with schematic capture and circuit board design
VERIFICATION ENGINEER OVM/UVM Location: California
Proficiency
in advanced Verification techniques, at both a block and system level, to work
with the design engineering team to support excellence in design principles and
practice.
Knowledge and experience performing timing analysis/debug and implementing design improvements.
Knowledge and experience performing timing analysis/debug and implementing design improvements.
RTL Design Engineer Location
: Colorado
Experience: 5-6 Years
LEAD RTL DESIGN ENGINEER Location
: Idaho
lead role for the RTL Design Engineer.
- block level spec, write RTL. Blocks will reside on AHB/AXI bus so
- familiarity with these bus structures is desired.
- ARM M3/R4/R5 experience nice to have Verilog Write test benches
- block level spec, write RTL. Blocks will reside on AHB/AXI bus so
- familiarity with these bus structures is desired.
- ARM M3/R4/R5 experience nice to have Verilog Write test benches
LOGIC VERIFICTION ENGINEER Location : Massachusetts
Candidates should also have experience with RTL simulators,
VCS preferred, experience specifying and developing test bench components,
specifying, developing, and debugging functional tests, and experience
specifying, implementing and analyzing functional coverage.
PHYSICAL DESIGN ENGINEER Location:
Colorado
SOC Encounter P&R, PrimeTime, Apache, Caliber
Block builds that range in size from 100K to 1500K placed instances with flat hierarchy including embedded IP. Note this may also include padframe blocks.
Individual engineer ownership to include 1-6 blocks depending on complexity (gate count, # clock domains, congestion, timing closure, etc….)
Block builds that range in size from 100K to 1500K placed instances with flat hierarchy including embedded IP. Note this may also include padframe blocks.
Individual engineer ownership to include 1-6 blocks depending on complexity (gate count, # clock domains, congestion, timing closure, etc….)
To Apply and for detailed JDs:
Please send your profiles at artibhatia@embeddedcareers.com and or get registered at embeddedcareers.com.
Arti
Bhatia
Marketing Executive
Embedded Careers
No comments:
Post a Comment