Opportunity for a Physical Design Lead(Magma Expert, P&R, PrimeTime). Experience: 5-10 years. Location: USA / California Apply @ http://embeddedcareers.com/login.php

Position Title		Lead Physical Design Engineer (Magma Expert, P&R, PrimeTime)
Product Domain Expertise		Semiconductor
Skill Category		ASIC Design
Position Type		Contract Employment
Estimated Duration of Contract		> 12 months
Hire Timeframe		Immediate
Job Location		USA / California,
Experience Level (Years)		8-10 Years
Salary		DoE
Qualification		Magma
Mandatory Skills		Magma
Desirable Skills		Magma
Job Description
opportunity for a Physical Design Lead to join our team and work onsite at our customer’s location in Sunnyvale, California. As technical lead you will execute physical design, place and route, and timing closure of very large complex SoCs. The project duration is 8-12 months. Skills required: • Must have strong Magma tools experience and PrimeTime • Must have strong Place and Route experience • Physical synthesis / Floorplanning / Test insertion, Clock tree synthesis / Parasitic extraction, Static timing analysis • Post-layout timing closure • Experience with top-level design tasks • Generate accurate timing constraints for complex SOC designs that have a large number of clocks and multiple operational modes • Have done multiple chips; multiple tape outs and designs • Good knowledge of HDL and digital design techniques is essential • Experience with the UNIX or LINUX • Write/debug PERL and TCL scripts Education and years of experience: • BSEE required, MSEE preferred. • 5-10+ years experience Additional Information: ** Candidates MUST be US Citizen or US Permanent Resident (green card holder) or able to obtain a TN visa (for citizens of Canada and Mexico only) or require H1B transfer only.

Openings for Design Manager : 8 yrs Worked on protocols like AMBA AHB/AXI, MIPI, PCI Express, SATA, USB. Location :Bangalore, Delhi, Noida, gurgaon, delhi ncr. Apply @ http://embeddedcareers.com/login.php

Position Title		Design Manager : 8 yrs
Product Domain Expertise		Semiconductor
Skill Category		ASIC Design
Position Type		Permanent Employment
Hire Timeframe		Immediate to 30 days
Job Location		India / Bangalore, Delhi, Noida, gurgaon, delhi ncr
Experience Level (Years)		8-10 Years
Salary		As Per Industry Standards
Qualification		BE/B.Tech./MS/M.Tech. (Electronics or Electronics & Communication)
Mandatory Skills		HVL (System Verilog, Vera, Specman, E, VMM, OVM, UVM)
Desirable Skills		Worked on protocols like AMBA AHB/AXI, MIPI, PCI Express, SATA, USB
Job Description
Core Competencies: Worked on SoC level testbench and verification environment Testbench architecture, coding and good understanding of design issues in RTL Testbench generation, testvector creation, simulations, gate level simulations Hands on with System Verilog and Assertion based verification methodology  Atleast 4years of experience on HVL (System Verilog, Vera, Specman, E, VMM, OVM, UVM) Should be able to work independently and able to guide other team members Problem solving capabilities with leadership qualities Should have managed a team of 10 or more engineers
Desired Profile / Roles
Simulation Tools: NCSIM/VCS/ModelSim/Questa Added Advantage: Knowledge of RTL coding styles  Low power verification (UPF/CPF) would be an added plus Experience on System C would be an added plus Worked on protocols like AMBA AHB/AXI, MIPI, PCI Express, SATA, USB

Openings forSr. Design & Design Engineers Exp: 2-5(System Verilog, Vera, Specman, E, VMM, OVM, UVM) years.Location: Bangalore, Delhi NCR, Noida. . Apply @ http://embeddedcareers.com/login.php

Position Title		Sr. Design Engineer & Design Engineer: 2 to 5 yrs
Product Domain Expertise		Semiconductor
Skill Category		ASIC Design
Position Type		Permanent Employment
Hire Timeframe		Immediate to 30 days
Job Location		India / Bangalore, Delhi, Noida, Delhi NCR, Gurgaon
Experience Level (Years)		3-5 Years
Salary		As Per Industry Standards
Qualification		BE/B.Tech./MS/M.Tech. (Electronics or Electronics & Communication)
Mandatory Skills		(System Verilog, Vera, Specman, E, VMM, OVM, UVM) Should be able to work independently and able to guide others
Desirable Skills		Testbench generation, testvector creation, simulations, gate level simulations
Job Description
Core Competencies:   Worked on SoC level testbench and verification environment Testbench architecture, coding and good understanding of design issues in RTL Testbench generation, testvector creation, simulations, gate level simulations Hands on with System Verilog and Assertion based verification methodology  Atleast 2years of experience on HVL (System Verilog, Vera, Specman, E, VMM, OVM, UVM) Should be able to work independently and able to guide others
Desired Profile / Roles
Simulation Tools: NCSIM/VCS/ModelSim/Questa Added Advantage: Knowledge of RTL coding styles  Low power verification (UPF/CPF) would be an added plus Experience on System C would be an added plus Worked on protocols like AMBA AHB/AXI, MIPI, PCI Express, SATA, USB

Openings for Silicon Validation of Analog IP in SOC 4 to 8 yrsJob Location: Bangalore, Delhi NCR, Noida. . Apply @ http://embeddedcareers.com/login.php

Position Title		Silicon Validation of Analog IP in SOC 4 to 8 yrs
Product Domain Expertise		Semiconductor
Skill Category		ASIC Design
Position Type		Permanent Employment
Hire Timeframe		Immediate to 30 days
Job Location		India / Bangalore, Delhi, Noida,
Experience Level (Years)		3-5 Years
Salary		As Per Industry Standards
Qualification		BE/ BTech (Electronics/ Electrical/ Electronics & Comm) : MSc (VLSI/ Electronics/ Electrical/ Electronics & Comm) : MS or MTech would be preferred
Mandatory Skills		VLSI Testing - Post Silicon Validation of 22nm, 32nm, 45nm, 65nm and 90nm Analog IPs
Desirable Skills
Job Description
Core Competencies: -    VLSI Testing - Post Silicon Validation of 22nm, 32nm, 45nm, 65nm and 90nm Analog IPs -    Programming Languages: LABVIEW, C, C++, Assembly -    Candidate should be able to setup LabVIEW based automation for Post Silicon Validation -    Signal Integrity Analysis using Agilent-ADS and/ or Cadence - Allegro PCB designer -    Candidate should have defined, developed and executed Test Plans for Analog Electrical Characterization of advanced
Desired Profile / Roles
CMOS I/O’s, Compensation blocks, DDR, BIDIRS, LVDS, PLL, Power Management Block, LDO, ADC, etc. -    Perform Analog electrical characterization, Signal measurements with the ATE -    Familiarity with High BW Oscilloscope, Pattern & Pulse Generator, Time Domain Reflectometry, Eye Analysis

Openings for Engineers with 3 to 5 yrs of Exp. in Scan insertion and DRC cleanup. Job Location: Bangalore, Delhi NCR, Noida. . Apply @ http://embeddedcareers.com/login.php

Dear Admin, A new job has been posted by True chip solution Pvt Ltd.. Job Details : Position Title   Engineers with 3 to 5 yrs of Exp. in Scan insertion and DRC cleanup Product Domain Expertise   Semiconductor Skill Category   Board Design Position Type   Permanent Employment Hire Timeframe   Immediate to 30 days Job Location   India / Bangalore, Chennai, Delhi, Noida, Experience Level (Years)   3-5 Years Salary     As Per Industry Standards Qualification     BE/ BTech (Electronics/ Electrical/ Electronics and Communication) MS or MTech would be preferred Mandatory Skills   Scan insertion and DRC cleanup, JTAG or P1500 Desirable Skills    Job Description      The candidate is expected to have worked on : -    Scan insertion and DRC cleanup -    Pattern generation for Stuck-At, delay test, iddq, path delay and fault grading. -    Memory testing. Should also know the algorithms. Should also have knowledge about diagnostics. -    JTAG or P1500 or other interface mechanism Desired Profile / Roles      Desirable competencies  The candidate is expected to have exposure to : -    Compression tools is highly desirable -    LBIST, mixed-signal testing, logic equivalence -    Writing testbenches and should be capable of writing RTL code for DFT blocks as and when required. -    Bridge fault detection is desirable -    ATE experience is an added advantage

Openings for Engineers with 5 to 7 yrs Exp. of Leading DFT team for at least two SOCs. Job Location: Bangalore, Delhi NCR, Noida. . Apply @ http://embeddedcareers.com/login.php

Position Title		Engineers with 5 to 7 yrs Exp. of Leading Led a DFT team for at least two SOCs
Product Domain Expertise		Semiconductor
Skill Category		ASIC Design
Position Type		Permanent Employment
Hire Timeframe		Immediate to 30 days
Job Location		India / Bangalore, Chennai, Delhi, Noida,
Experience Level (Years)		5-6 Years
Salary		As Per Industry Standards
Qualification		BE/ BTech (Electronics/ Electrical/ Electronics and Communication) MS or MTech would be preferred
Mandatory Skills		DFT team for at least two SOCs scan, atpg, structures for delay test,
Desirable Skills		LBIST, mixed-signal testing and post-silcon bring up
Job Description
Core competencies: The candidate should have : -    Led a DFT team for at least two SOCs -    A hold over the complete flow i.e. scan, atpg, structures for delay test,      coverage analysis, memory testing, netlist simulations and pattern delivery. -    Ability to decide on the take decision on approaches -    Ability to decide on the the schedule and effects on it due to different approaches. -    Exposure to LBIST, mixed-signal testing and post-silcon bring up  -    Exposure to timing or synthesis and should be able to decide on the constraints for the same. -    Ability to mentor the junior team members and drive them for achieving best results. -    Ability to communicate and discuss options with the client

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