Openings for Engineers with 3 to 5 yrs of Exp. in Scan insertion and DRC cleanup. Job Location: Bangalore, Delhi NCR, Noida. . Apply @ http://embeddedcareers.com/login.php

Dear Admin, A new job has been posted by True chip solution Pvt Ltd.. Job Details : Position Title   Engineers with 3 to 5 yrs of Exp. in Scan insertion and DRC cleanup Product Domain Expertise   Semiconductor Skill Category   Board Design Position Type   Permanent Employment Hire Timeframe   Immediate to 30 days Job Location   India / Bangalore, Chennai, Delhi, Noida, Experience Level (Years)   3-5 Years Salary     As Per Industry Standards Qualification     BE/ BTech (Electronics/ Electrical/ Electronics and Communication) MS or MTech would be preferred Mandatory Skills   Scan insertion and DRC cleanup, JTAG or P1500 Desirable Skills    Job Description      The candidate is expected to have worked on : -    Scan insertion and DRC cleanup -    Pattern generation for Stuck-At, delay test, iddq, path delay and fault grading. -    Memory testing. Should also know the algorithms. Should also have knowledge about diagnostics. -    JTAG or P1500 or other interface mechanism Desired Profile / Roles      Desirable competencies  The candidate is expected to have exposure to : -    Compression tools is highly desirable -    LBIST, mixed-signal testing, logic equivalence -    Writing testbenches and should be capable of writing RTL code for DFT blocks as and when required. -    Bridge fault detection is desirable -    ATE experience is an added advantage

Openings for Engineers with 5 to 7 yrs Exp. of Leading DFT team for at least two SOCs. Job Location: Bangalore, Delhi NCR, Noida. . Apply @ http://embeddedcareers.com/login.php

Position Title		Engineers with 5 to 7 yrs Exp. of Leading Led a DFT team for at least two SOCs
Product Domain Expertise		Semiconductor
Skill Category		ASIC Design
Position Type		Permanent Employment
Hire Timeframe		Immediate to 30 days
Job Location		India / Bangalore, Chennai, Delhi, Noida,
Experience Level (Years)		5-6 Years
Salary		As Per Industry Standards
Qualification		BE/ BTech (Electronics/ Electrical/ Electronics and Communication) MS or MTech would be preferred
Mandatory Skills		DFT team for at least two SOCs scan, atpg, structures for delay test,
Desirable Skills		LBIST, mixed-signal testing and post-silcon bring up
Job Description
Core competencies: The candidate should have : -    Led a DFT team for at least two SOCs -    A hold over the complete flow i.e. scan, atpg, structures for delay test,      coverage analysis, memory testing, netlist simulations and pattern delivery. -    Ability to decide on the take decision on approaches -    Ability to decide on the the schedule and effects on it due to different approaches. -    Exposure to LBIST, mixed-signal testing and post-silcon bring up  -    Exposure to timing or synthesis and should be able to decide on the constraints for the same. -    Ability to mentor the junior team members and drive them for achieving best results. -    Ability to communicate and discuss options with the client

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Design Engineer 2-6 years   True chip solution Pvt Ltd. Location : Bangalore, Delhi Experience : 2-3 Years Posted on: 01 Jun 2012 Sr. Design Engineer : 3 to 5 yrs   True chip solution Pvt Ltd. Location : Bangalore, Delhi, Noida, Delhi NCR, Gurgaon Experience : 3-5 Years Posted on: 01 Jun 2012 Design Manager : 8 yrs   True chip solution Pvt Ltd. Location : Bangalore, Delhi, Noida, gurgaon, delhi ncr Experience : 8-10 Years Posted on: 01 Jun 2012 Silicon Validation of Analog IP in SOC 4 to 8 yrs   True chip solution Pvt Ltd. Location : Bangalore, Delhi, Noida Experience : 3-5 Years Posted on: 01 Jun 2012 Engineers with 3 to 5 yrs of Exp. in Scan insertion and DRC cleanup   True chip solution Pvt Ltd. Location : Bangalore, Chennai, Delhi, Noida Experience : 3-5 Years Posted on: 01 Jun 2012 Engineers with 5 to 7 yrs Exp. of Leading Led a DFT team for at least two SOCs   True chip solution Pvt Ltd. Location : Bangalore, Chennai, Delhi, Noida Experience : 5-6 Years Posted on: 01 Jun 2012 ENTRY LEVEL DESIGN ENGINEERS fresh 2012passouts   Freescale Semiconductor Location : Noida Experience : Fresher Posted on: 31 May 2012

Career opportunity for freshers (2012) as core Design Engineer for Electronics & Communication Engineering B.E/B.Tech from IIT/NIT/REC & other Premier colleges , M.tech-(IIT/IISC) 2012 Apply @ http://embeddedcareers.com/login.php

Opening for Lead Physical Design Engineer (Magma Expert, P&R, Prime Time) Experience: 8-10 Years. Location:USA / California, Apply @ http://embeddedcareers.com/login.php

Job Details : Position Title Lead Physical Design Engineer (Magma Expert, P&R, PrimeTime) Product Domain Expertise Semiconductor Skill Category ASIC Design Position Type Contract Employment Estimated Duration of Contract  > 12 months Hire Timeframe Immediate Job Location USA / California, Experience Level (Years) 8-10 Years Salary   DoE Qualification   Magma Mandatory Skills Magma Desirable Skills  Magma Job Description Encore Semi ( www.encoresemi.com ) has an immediate opportunity for a Physical Design Lead to join our team and work onsite at our customer’s location in Sunnyvale, California. As technical lead you will execute physical design, place and route, and timing closure of very large complex SoCs. The project duration is 8-12 months. Skills required: • Must have strong Magma tools experience and PrimeTime • Must have strong Place and Route experience • Physical synthesis / Floorplanning / Test insertion, Clock tree synthesis / Parasitic extraction, Static timing analysis • Post-layout timing closure • Experience with top-level design tasks • Generate accurate timing constraints for complex SOC designs that have a large number of clocks and multiple operational modes • Have done multiple chips; multiple tape outs and designs • Good knowledge of HDL and digital design techniques is essential • Experience with the UNIX or LINUX • Write/debug PERL and TCL scripts Education and years of experience: • BSEE required, MSEE preferred. • 5-10+ years experience Candidates MUST be US Citizen or US Permanent Resident (green card holder) or able to obtain a TN visa (for citizens of Canada and Mexico only) or require H1B transfer only.

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Latest Jobs

ENTRY LEVEL DESIGN ENGINEERS fresh 2012passouts   Freescale Semiconductor Location : Noida Experience : Fresher Posted on: 31 May 2012 Lead Physical Design Engineer (Magma Expert, P&R, PrimeTime)   Encore Semi LLC Location : California Experience : 8-10 Years Posted on: 31 May 2012 Senior Software Engineer (VOIP Application Development)   L&T Integrated Engineering Services Location : Bangalore Experience : 5-6 Years Posted on: 26 May 2012 Senior Software Engineer (VOIP - Windows Team)   L&T Integrated Engineering Services Location : Bangalore Experience : 3-5 Years Posted on: 26 May 2012 Analog/Mixed-Signal Design Engineer (ADC, ADE)   Encore Semi LLC Location : California Experience : 8-10 Years Posted on: 23 May 2012 Python Scripting Engineer   Dexcel Electronics Designs Location : Bangalore Experience : 3-5 Years Posted on: 22 May 2012 Lead Place & Route Engineer for 40nm projects   Encore Semi LLC Location : California Experience : 8-10 Years Posted on: 22 May 2012

Career opportunity for freshers (2012) as core Design Engineer for Electronics & Communication Engineering B.E/B.Tech from IIT/NIT/REC & other Premier colleges , M.tech-(IIT/IISC) 2012 Apply @ http://embeddedcareers.com/login.php

Latest Jobs

ENTRY LEVEL DESIGN ENGINEERS fresh 2012passouts   Freescale Semiconductor Location : Noida Experience : Fresher Posted on: 31 May 2012 Senior Software Engineer (VOIP Application Development)   L&T Integrated Engineering Services Location : Bangalore Experience : 5-6 Years Posted on: 26 May 2012 Senior Software Engineer (VOIP - Windows Team)   L&T Integrated Engineering Services Location : Bangalore Experience : 3-5 Years Posted on: 26 May 2012 Analog/Mixed-Signal Design Engineer (ADC, ADE)   Encore Semi LLC Location : California Experience : 8-10 Years Posted on: 23 May 2012 Python Scripting Engineer   Dexcel Electronics Designs Location : Bangalore Experience : 3-5 Years Posted on: 22 May 2012 Lead Place & Route Engineer for 40nm projects   Encore Semi LLC Location : California Experience : 8-10 Years Posted on: 22 May 2012 Senior Hardware Design Engineer position in San Diego   Encore Semi LLC Location : California Experience : 8-10 Years Posted on: 17 May 2012