Opening for Physical Design Engineer Experience 5+ years Apply @ http://embeddedcareers.com/

• BE|ME|BTech|MTech
  Understanding Verilog HDL
• Understanding Deep Submicron effects such as 90nm and below
• Understanding OCV, DFM, DFY
• Excellent Block level and Full-chip physical design skills
• Self-motivated, leadership skills and experience working with global teams
• Minimum 5 years of ASIC physical design experience
• Back ground of ASIC Physical Design: Floor planning, Clock Tree Synthesis, P&R, extraction, EM/IR Drop Analysis, timing and Signal Integrity closure, physical verification, low power implementation etc
• Hands on experience and expertise in Cadence, Synopsys, Magma or Mentor Physical Implementation Tools
• Should have participated in a minimum of 3 fullchip tapeouts.

 To Apply and for detailed JDs: Please Send your profiles at artibhatia@embeddedcareers.com and or get registered at embeddedcareers.com.

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Arti Bhatia                                                                    

Marketing Executive

Embedded Careers

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