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Sunday, June 17, 2012

Hiring Asic Design, Embedded, and Firmware Engineers. Experience: 1 -10 years. Locations: Bangalore, Noida, Delhi NCR, Chennai, Hyderabad. Apply @ http://embeddedcareers.com/login.php




EmbeddedCareers.com has been looking for Asic Design, Embedded and Firmware engineers for some great openings with us. You can apply to these jobs @ http://embeddedcareers.com/login.php or send profiles at artibhatia@embeddedcareers.com.

Embedded Engineers (2-8 years): With good knowledge of C, C++, on Linux Platform. Skills: I2C, SPI, UART, USB, device Driver, BSP development. Board Bring up.
Device Driver, BSP development. Very Good C Programming, Assembly Language Programming.

Good Understanding of CPU Architecture ARM, MIPS and PowerPC Hardware interfaces: Nand/NOR Flash, DDR SDRAM, PCI (variants), Ethernet MAC/PHY Protocols : I2C, SPI, UART, USB, device Driver, BSP development.

Board Bring up. Boot loader Porting/development. Hardware Diagnostics Development. Linux Porting, Linux Kernel and microcontroller Concepts. Customizing kernel + Porting + developing applications Linux Device Driver Development (Character devices) Good Concepts of Network Drivers File systems concepts.




ASIC Design Engineers (1-10 years): Multiple requirements across domain and all levels of Expertise.

Hard Macro, Block level implementation,3 yrs in PD implementation, Talus or ICC or PTSI. Take metrics from designers and find a block and placement of PTSI Target companies—All semiconductor companies, Freescale, ST Micro, AMD

TOP level CTS routing resource//knowing basics of CTS//4yrs//Olympus tool(1 to 2yrs) or TALUS or ICC-not a preference// Data base from main resource and to multiple triages//verification, physical verification Mentor graphics AE’s, Magma

Encounter/top level activity with Scripting experience, manual editing//specific tool-first encounter, special DB commands//Engineer who work on floor plan


Exposure to LBIST, mixed-signal testing and post-silcon bring up, LBIST, mixed-signal testing and post-silcon bring up

Scan insertion and DRC cleanup, JTAG or P1500,   Pattern generation for Stuck-At, delay test, iddq, path delay and fault grading. Writing testbenches and should be capable of writing RTL code for DFT blocks as and when required. 

HVL (System Verilog, Vera, Specman, E, VMM, OVM, UVM), Worked on protocols like AMBA AHB/AXI, MIPI, PCI Express, SATA, USB
Mandatory Skills:

(System Verilog, Vera, Specman, E, VMM, OVM, UVM) Should be able to work independently and able to guide others
Desirable Skills 

Testbench generation, testvector creation, simulations, gate level simulations
Job Description


 Core Competencies: 

Worked on SoC level testbench and verification environment
Testbench architecture, coding and good understanding of design issues in RTL
Testbench generation, testvector creation, simulations, gate level simulations
Hands on with System Verilog and Assertion based verification methodology 
Atleast 2years of experience on HVL (System Verilog, Vera, Specman, E, VMM, OVM, UVM)
Should be able to work independently and able to guide others



You can collect Detailed JDS  @  http://embeddedcareers.com/index.php or mail us at artibhatia@embeddedcareers.com


Arti Bhatia                                                                    
Marketing Executive
Embedded Careers

1 comment:

  1. These steps, implemented with a level of skill common in the industry, almost always produce a final device that correctly implements the original design, unless flaws are later introduced by the physical fabrication process. IC Design

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