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Sunday, May 13, 2012

Openings for ASIC Front End Lead, Asic Verification Engineers. Experience 3- 8years Job Locations India & USA Apply @ http://embeddedcareers.com/


1)     ASIC FRONT-END LEAD Location: Bangalore
BE/BTech/ME/MTech  5-8 Years
Working experience in Verilog
Experience in ASIC implementation – Synthesis/DFT, STA, LEC
Experience with Processor based fullchip design like ARM, Tensilica, MIPS etc. based SoCs
Experience in leading and driving the team to deliver as per work plan
Experience in interfacing with customer, reviewing project and reporting to custo
Experience with and understanding of ASIC development, system architecture, and system software for system-on-chip products using an embedded processor
Knowledge of ASIC P&R Flow
Work experience in bus protocols like AMBA, OCP, AXI etc.
Good Communication and Interpersonal Skills


2)     ASIC Verification Engineer (SV+OVM/VMM/UVM with 4 to 7 Years)
Job Location:SANJOSE,USA
QUALIFICATIONS: BE/B.Tech/ME/M.Tech

Proficiency in one or more HVL's a must (System Verilog).
Strong domain knowledge on one or more - PCIe , USB, Ethernet, ARM, AHB/AXI, AMBA. Should have worked on SOC verification on at least one project with constrained random methodology (eRM/VMM/OVM). Must be expert in building a verification env with any of the above methodology, writing and debugging test cases. Good in concepts Code coverage and functional coverage. Expertise in Verilog and / or VHDL is desired
Working knowledge of any one scripting language like Perl, Python, Unix Make, Unix Shell Scripts etc.

3)     ASIC Verification Engineer Location Bangalore
Years of Experience: 3-15 Years                                                                                                                                    
Qualification: BE/ME/BTECH/MTECH
Job Location: Bangalore
 Proficiency in one or more HVL's a must (System Verilog,Specman, Vera, e,).
 Strong domain knowledge on one or more - PCIe,USB, Ethernet, ARM, AHB/AXI, AMBA
 Should have worked on SOC verification on at least one project with constrained random    methodology (eRM/VMM/OVM).
 Must be expert in building a verification env with any of the above methodology, writing and debugging test cases.
 Good in concepts Code coverage and functional coverage.
 Expertise in Verilog and / or VHDL is desired
 Working knowledge of any one scripting language like Perl, Python, Unix Make, Unix Shell Scripts etc.

To Apply and for detailed JDs: Please send your profiles at artibhatia@embeddedcareers.com and or get registered at embeddedcareers.com.

Arti Bhatia                                                                    
Marketing Executive
Embedded Careers

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