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Thursday, May 3, 2012

Opening for Verification Engineer-OVM /UVM. Experience: 5-6years. Location : California USATo Apply and for detailed JDs: Please send your profiles at artibhatia@embeddedcareers.com and or get registered at embeddedcareers.com

Product Domain Expertise  : Semiconductor.
Skill Category : ASIC Design
System Verilog, OVM/UVM

--> Proficiency in advanced Verification techniques, at both a block and system level, to work with the design engineering team to support excellence in design principles and practice.
--> Knowledge and experience performing timing analysis/debug and implementing design improvements.
--> Experience in developing block and chip level test benches, test plan creation.
--> Experience with OVM/UVM, object oriented design principles, Mentor Questasim SV, Power Aware, SVA assertion.
--> The ability to work with firmware teams in developing co-simulation environments and system models.

2 Positions for 6+ Months in San Jose, CA
H1 B Welcome to apply.
Please apply only if physcially present in US.
To Apply and for detailed JDs: Please send your profiles at artibhatia@embeddedcareers.com and or get registered at embeddedcareers.com.



Arti Bhatia                                                                    
Marketing Executive
Embedded Careers
https://www.facebook.com/embeddedcareers


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