Looking for Senior Manager (Asic Design) Location Hyderabad...

Job Requirements and Skills:
• B.E/B.Tech/M.E/M.Tech in Electrical/Electronic Engineering
• Minimum 10-17  years experience in ASIC Design Verification
• Experience in Graphics or Multimedia domains is a plus
• Must have excellent knowledge of ASIC Design Flow
• Experience in developing complex  test bench/model in verilog, System verilog or SystemC
• Experience with coverage-based verification methodology
• Experience in writing test plans and test cases
• Excellent debug skills in both functional and gate level simulations are must.
• Experience in random test generation, coverage analysis, failure debug, formal equivalency checking, and Assertions (PSL, SVA)
• Strong Verilog, System Verilog, PLI interface, SystemC or C/C++, Perl/shell scripts or Vera programming skills.
• Experience with emulation based verification and/or simulation acceleration techniques an asset
• Must have good communication skills and the ability and desire to foster a team environment.

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Senior Manager   Adecco India Location : Hyderabad Experience : 10-15 Years