Physical Design, STA &Synthesis, Flow and Methodology (Staff-II/Sr.Staff/Principal/Sr. Principal) Exp: 3-15 years. Send your profiles at artibhatia@embeddedcareers.com

 

Please send your profiles at artibhatia@embeddedcareers.com or apply at http://www.embeddedcareers.com/

Job Description:  1. Physical Design Job Description: Positioned in a growing LTE/4G market, and projecting a very aggressive processor roadmap, Broadcom is looking for Technical Lead physical design engineers for the complex MultiMode wireless (4G,3G and 2G) modem baseband ASICs working on the latest process technology nodes.Essential Functions: Self driven individual will be responsible for activities related to full chip floor plan, power grid design, IO ring design, clock tree design, place and route of full chip and critical blocks, cross talk analysis, IR drop analysis, timing optimization, physical verification, and interfacing to cross functional teams for complex low power and hierarchical chips in advance technology nodes.Candidate should have strong basic concepts to over challenges in the different part of Physical design and should be able to overcome those based on different experiments and data. Should be able to technically lead the team for delivery of technical milestones.Experience in RTL to GDSII flow with involvement in multiple tapeouts. Should have handled full chip floor plan and timing closure for multi-million gate designs. Should have been involved in tape-out the chip in the advance technology nodes like 28nm and below/40nm. Should be able to come up with the ideas for the team for the better flow in advance node process. Any interaction with foundry for the advance process node is a plus. A good hands on exposure to that big hier design is a required.Good experience in technically leading a team of physical design engineers and interfacing with cross functional teams Strong communication and analytical skills 2. STA &Synthesis Job Description: Positioned in a growing LTE/4G market, and projecting a very aggressive processor roadmap, Broadcom is looking for Technical Lead in the timing and synthesis area for the complex Multimode wireless (4G,3G and 2G) modem baseband ASICs working on the latest process technology nodes Essential Functions: Self driven individual will be responsible for activities related to full chip and block timing closure and sign-off, synthesis, equivalence checks. The person should be able to work with design team and the physical design team to device the multiple ways to close the timing of different timing critical sub design or functionalities. Person should also be able to see synthesis and STA challenges with advance technology nodes and setup methodologies/guideline and sign-off criteria with enough data and experiments. Should be able to technically lead the team for delivery of tasks as well as the interface with design and Physical design Desired Skills & Experience Experience in timing/synthesis flow with involvement in multiple tape outs. Should have handled timing closure for multi-million gate designs. Should have been involved in tape-out the chip in the advance technology nodes like 28nm and below/40nm. Should be able to come up with the ideas for the team for the better flow in advance node process. Brief break-up of the skills is below Work with RTL design teams in understanding the design and developing the timing constraints both at block and SOC level, decision on timing modes and the corners .2. Should had Synthesized the blocks and SOC with best QOR. Knows synthesis concepts in and out, should had worked on the synthesis methodology/recipes .3. Should have Worked out the sign-off constraints/modes/corners and come up with the sign-off timing closure methodology. Should had worked on the signoff timing closure and aware. 3. Flow and Methodology Job Description: The candidate will be responsible for developing methodology/tools that will automate the physical   design/timing closure flow to improve implementation turnaround time, QOR and efficiency of deliverables. Job Requirements experience working within Physical Design/STA/Synthesis CAD Methodology for a leading semiconductor company is required. Should have worked on end to end flow and have strong working knowledge of issues/methodologies in advance process nodes of 20nm or below Strong Place and Route tools knowledge is required: Atop/Synopsys/Magma/Cadence. Experience in using Synthesis and Timing Closure methodology. Knowledge of a)      Power reduction b)      Clock Tree optimization c)       High performance design closure d)      Low Power implementation e)      Area reduction Must have strong scripting skills - PERL/TCL/Makefile

Desired Profile / Role :  1. Sr. Design Manager (ASIC/SoC Design) - 15+Yrs. 2. 4G Architecture Modeling-10+yrs. 3. Modem Design Manager (ASIC/SoC Design) – 10 to 15yrs. 4. Principal/Sr. Principal (Physical Design) - 10+yrs. 5. Sr. Staff (Physical Design)-5 to 10yrs. 6. Staff-II (Physical Design)-2 to 5yrs. 7. Principal/Sr. Principal (STA/Synthesis) - 10+yrs. 8. Sr.Staff (STA/Synthesis) - 5 to 10yrs. 9. Staff-II/Sr.Staff (RTL Design) – 2 to 10yrs. 10. Sr. Staff/Principal (ASIC/FPGA Package Design) – 5+yrs 11. Staff-II/Sr.Staff/Principal (Physical Layer)- 2to15yrs. 12. Staff-II/Sr.Staff/Principal (ASIC Verification) – 4to 10yrs 13. Associate Technical Director (16+yrs). 14. Principal/Sr.Principal (RTL Design)-10+yrs 15. Test Automation Engineer (Board Design)-5+yrs Hiring For Broadcom.

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Hiring for tier-1 semiconductor vendor "Connecting everything" is looking for right resource in ASIC domain. Exp: 5+ years. Please send your profiles at artibhatia@embeddedcareers.com Apply @ http://embeddedcareers.com/

Openings Input Output Layout & Verification, PCB Schematic Design Layout/Field Applications Engineers, Locations: USA, Malaysia & India. Exp: 2 -10 years. Mail @ artibhatia@embeddedcareers.com

Openings Input Output Layout & Verification, PCB Schematic Design Layout/Field Applications Engineers, Locations: USA, Malaysia & India. Exp: 2 -10 years. Mail @ artibhatia@embeddedcareers.com

Hi All.

Currently we are looking for

To Apply: Just logon to   http://embeddedcareers.com/. Or Send your profiles at artibhatia@embeddedcareers.com

1)     PCB Schematic Design Layout/Field Applications Engineer (Michigan, USA) Experience: 6-8 years

Domain (Automotives)

Mandatory Skills: Schematic Capture, PCB Layout, Circuit Simulation, Circuit Analysis

Desirable Skills: Cadence-based verification tools, Modeling, Mixed-signal verification

Job Description  

                Circuit Design for new LSI products and customer specific applications

·         

2)     Input Output Layout Engineer (Bangalore) Experience: 2-4 years

Mandatory Skills: IO library development-USB layout, HSTL layout, SSTL layout, GPIO layout, MFIO layout, LVDS layout

3)     Verification Engineer (Malaysia and Bangalore) Experience: 2-8years

Verilog/VHDL Language Proficiency

-     Hands-on experience in one of the Methodologies – OVM, VMM, AVM, UVM using SystemVerilog

-     Working Experience in one of the Protocols like USB, PCIe, DDR, SATA etc.

4) System Verilog / Specman / Vera Verification Engineer 
Job Location : Bangalore
Experience : 3 - 10 years
Job Description : BFMs Development, Test Case Development, Module and SOC level verification and ARM processor knowledge. Expertise in debugging tools is must. Good knowledge on code coverage, functional coverage tools, USB, PCIE and AHB/AXI.

5) SoC Level Physical Designer 
Job Location : Bangalore 
Experience : 3 - 8 years
Job Description : Place & Route (PnR), CTS, Floor Planning, Timing closure, Power Planning, IO planning, Synthesis, STA, MAGMA, ICC, Primetime, PTSI, Design Compiler, Apache, Calibre

6) DFT lead Engineer 
Exp: 3-8yrs
Location: Bangalore
Job Description : Strong knowledge of DFT including JTAG, MBIST, scan, on-chip scan compression, fault models, ATPG, and fault simulation and AC scan for at speed testing, Expertise in industry standard EDA tools for DFT such as DFTAdvisor, fastscan/TestKompress, TetraMax, Dft compiler

7) Analog Layout
Exp:2-9 years
Location: Banglore
Job description: Analog Mixed-Signal layout and verification for different complex analog circuits in 90nm node or lesser. Knowledge of half cell Tool Experience like Cadence Virtuso ,Vxl and Virtuoso, Schematic Composer, and verifications tools including Assura, Mentor/Synopsys Calibre /Hercules LVS, DRC, STarRC for extraction

8) IO layout
Exp:2-5 years
Location: Banglore
Job description: ASIC IO Library Development . Should have experience on tools like cadence, virtuoso layout editor .Good Knowledge on Verification Tools like ASSURA , Mentor, Hercules, lVS , HSPICE. Experience on any one of the design tools like USB LAYOUT ,HSTL LAYOUT ,SSTL LAYOUT ,GPIO LAYOUT ,MFIO LAYOUT ,LVDS LAYOUT .

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Regards
Arti Bhatia 
Marketing Executive
Embedded Careers Email: artibhatia@embeddedcareers.com
LinkedIn: http://in.linkedin.com/in/artibhatia

http://embeddedcareers.com/ invites candidatures for Software/ Sr. S/W/ Lead & Sales & Marketing Engineers (Multimedia Mobile Platforms, Semiconductor, Embedded domains). Skills: C/C++, SpyGlass, EDA Tools, Logic/ Physical Synthesis, STA, Timing Optimization, Floorplanning, Place and Route. Locations: India & USA.

Hi All,

We have following posrions with us. You can apply to these jobs @ http://embeddedcareers.com/login.php or send profiles at artibhatia@embeddedcareers.com.

1)     Software Engineer - Multimedia and Applications. Experience: 3-5 Years. San Diego, CA

Strong C/C++ SW software, integration, testing skills required. Knowledge of real-time embedded Linux and Android debug/profiling tools. Knowledge of software integration, builds, and ability to debug problems. Experience with working on Mobile platforms, applications and Multimedia

2)     Software Engineer - Analyzers (2-4 years experience in developing C/C++ based core/application software) India / Noida

Skill required: • Very strong knowledge of C/C++ • Working knowledge of scripting languages such as Tcl, Perl etc • Excellent algorithm analysis skills and a good knowledge of data structures • Self-motivation and self-discipline • Knowledge of design-constraints is a big plus. The candidate should have 2-4 years experience in developing C/C++ based core/application software for popular tools preferably in the EDA industry. Knowledge of VHDL, Verilog would be required. Working knowledge of TCL and Perl is required

3) Lead Software Engineer - Low Power (3 to 6 years of relevant experience) India / Noida

Experience in developing on Linux with gcc # excellent algorithm analysis skills and a good knowledge of data structures. # Knowledge of STL # Extensive experience with debugging and tuning of C++ code is required # Extensive experience developing large, high-quality, object-oriented C++ based applications is required. Familiarity with ASIC design flow and the EDA tools and methodologies used therein. In-depth knowledge of Verilog/VHDL semantics from simulation and synthesis # Knowledge of EDA power tools. # scripting language

4) Consulting Software Engineer - SpyGlass Physical. 5 to 10 years of relevant experience. India / Noida

Very strong knowledge of complete RTL to Placement/Routing flow. Hands on experience of industry standard tools in the domains of Logic/ Physical Synthesis, STA, Timing Optimization, Floorplanning, Place and Route. Understanding of nanometer design challenges. Proficiency in writing and understanding Verilog, VHDL and Mixed language designs. Hands on experience of one or more of the reference ASIC Implementation flows. Working knowledge of Scripting languages such as Perl and Tcl, etc. will be a plus. Resourcefulness and effective business communication skills. Self-motivation, self-discipline and the ability to set personal goals and work consistently towards them in a dynamic environment. 5) Applications Engineering (5+ years experience in Applications Engineering and/or Frontend IC Design).  (Sales & Marketing) India / Bangalore Sound working knowledge of EDA front-end tools and their application. • Thorough knowledge of Verilog & VHDL hardware description languages.• Ability to write test cases/designs to reproduce tool behavior.• Knowledge and understanding of simulation/synthesis/verification flows.Prior experience on Atrenta SpyGlass® products will be added advantage. Assist Sales team in closing business by providing technical support during various stages of the sales cycle. Position is expected to perform product demonstrations, answer technical queries and help prospective customer to successfully and favorably evaluate  6) Sr.Product Engineer(5+ years) Noida Strong Verilog, c/c++, Specman E, object oriented programming skills * Excellent verbal and written communications skills * Strong interest and understanding of design and verification methodologies. 7) 5+ years of Experience in Power Estimation tool/other eda tool development. India / Bangalore Strong C/C++ programming and debugging skills * Strong in EDA data structures and algorithms. * Prior experience in EDA software development required.* Tcl/Perl programming skills preferred* Knowledge of Verilog / VHDL preferred * Familiarity with VLSI design process* Familiarity with rtl/gate level power estimation. You can apply to these jobs @ http://embeddedcareers.com/login.php or send profiles at artibhatia@embeddedcareers.com. Arti Bhatia                                                                     Marketing Executive Embedded Careers http://embeddedcareers.com  http://embeddedcareers.blogspot.com/. http://twitter.com/#!/CareersAtEC  https://www.facebook.com/embeddedcareers