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Physical Design, STA &Synthesis, Flow and Methodology (Staff-II/Sr.Staff/Principal/Sr. Principal) Exp: 3-15 years. Send your profiles at artibhatia@embeddedcareers.com

 

Please send your profiles at artibhatia@embeddedcareers.com or apply at http://www.embeddedcareers.com/

Job Description:  1. Physical Design Job Description: Positioned in a growing LTE/4G market, and projecting a very aggressive processor roadmap, Broadcom is looking for Technical Lead physical design engineers for the complex MultiMode wireless (4G,3G and 2G) modem baseband ASICs working on the latest process technology nodes.Essential Functions: Self driven individual will be responsible for activities related to full chip floor plan, power grid design, IO ring design, clock tree design, place and route of full chip and critical blocks, cross talk analysis, IR drop analysis, timing optimization, physical verification, and interfacing to cross functional teams for complex low power and hierarchical chips in advance technology nodes.Candidate should have strong basic concepts to over challenges in the different part of Physical design and should be able to overcome those based on different experiments and data. Should be able to technically lead the team for delivery of technical milestones.Experience in RTL to GDSII flow with involvement in multiple tapeouts. Should have handled full chip floor plan and timing closure for multi-million gate designs. Should have been involved in tape-out the chip in the advance technology nodes like 28nm and below/40nm. Should be able to come up with the ideas for the team for the better flow in advance node process. Any interaction with foundry for the advance process node is a plus. A good hands on exposure to that big hier design is a required.Good experience in technically leading a team of physical design engineers and interfacing with cross functional teams Strong communication and analytical skills 2. STA &Synthesis Job Description: Positioned in a growing LTE/4G market, and projecting a very aggressive processor roadmap, Broadcom is looking for Technical Lead in the timing and synthesis area for the complex Multimode wireless (4G,3G and 2G) modem baseband ASICs working on the latest process technology nodes Essential Functions: Self driven individual will be responsible for activities related to full chip and block timing closure and sign-off, synthesis, equivalence checks. The person should be able to work with design team and the physical design team to device the multiple ways to close the timing of different timing critical sub design or functionalities. Person should also be able to see synthesis and STA challenges with advance technology nodes and setup methodologies/guideline and sign-off criteria with enough data and experiments. Should be able to technically lead the team for delivery of tasks as well as the interface with design and Physical design Desired Skills & Experience Experience in timing/synthesis flow with involvement in multiple tape outs. Should have handled timing closure for multi-million gate designs. Should have been involved in tape-out the chip in the advance technology nodes like 28nm and below/40nm. Should be able to come up with the ideas for the team for the better flow in advance node process. Brief break-up of the skills is below Work with RTL design teams in understanding the design and developing the timing constraints both at block and SOC level, decision on timing modes and the corners .2. Should had Synthesized the blocks and SOC with best QOR. Knows synthesis concepts in and out, should had worked on the synthesis methodology/recipes .3. Should have Worked out the sign-off constraints/modes/corners and come up with the sign-off timing closure methodology. Should had worked on the signoff timing closure and aware. 3. Flow and Methodology Job Description: The candidate will be responsible for developing methodology/tools that will automate the physical   design/timing closure flow to improve implementation turnaround time, QOR and efficiency of deliverables. Job Requirements experience working within Physical Design/STA/Synthesis CAD Methodology for a leading semiconductor company is required. Should have worked on end to end flow and have strong working knowledge of issues/methodologies in advance process nodes of 20nm or below Strong Place and Route tools knowledge is required: Atop/Synopsys/Magma/Cadence. Experience in using Synthesis and Timing Closure methodology. Knowledge of a)      Power reduction b)      Clock Tree optimization c)       High performance design closure d)      Low Power implementation e)      Area reduction Must have strong scripting skills - PERL/TCL/Makefile

Desired Profile / Role :  1. Sr. Design Manager (ASIC/SoC Design) - 15+Yrs. 2. 4G Architecture Modeling-10+yrs. 3. Modem Design Manager (ASIC/SoC Design) – 10 to 15yrs. 4. Principal/Sr. Principal (Physical Design) - 10+yrs. 5. Sr. Staff (Physical Design)-5 to 10yrs. 6. Staff-II (Physical Design)-2 to 5yrs. 7. Principal/Sr. Principal (STA/Synthesis) - 10+yrs. 8. Sr.Staff (STA/Synthesis) - 5 to 10yrs. 9. Staff-II/Sr.Staff (RTL Design) – 2 to 10yrs. 10. Sr. Staff/Principal (ASIC/FPGA Package Design) – 5+yrs 11. Staff-II/Sr.Staff/Principal (Physical Layer)- 2to15yrs. 12. Staff-II/Sr.Staff/Principal (ASIC Verification) – 4to 10yrs 13. Associate Technical Director (16+yrs). 14. Principal/Sr.Principal (RTL Design)-10+yrs 15. Test Automation Engineer (Board Design)-5+yrs Hiring For Broadcom.

Openings for ASIC, Driver Development, BSP, SOC, FPGA and Embedded Engineers. Apply at http://embeddedcareers.com/. Rush your profiles at artibhatia@embeddedcareers.com.

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