EmbeddedCareers.com

Physical Design Engineers (2-12 years ) Apply @ http://embeddedcareers.com/

BE|BTech|ME|MTech
emc, physical design, soc, timing closure

Physical Design Engineer

You will be a part of the Group which is a global leader in the design, manufacturing and marketing of microcontrollers (MCUs) and embedded processors in the automotive, consumer and industrial markets. These products include 8-, 16- and 32-bit MCUs, 16-bit digital signal controllers (DSCs) and 32-bit microprocessors, as well as wireless connectivity solutions.

Your mission will be Driving ‘Zero Defect’ physical design solution with best in class benchmark for Area, Power, Performance, Quality and schedule

Your main duties will be:

•    Would be responsible for hands-on physical implementation and timing closure of core platforms and SoC's.
•    Evaluate and deploy the evolving physical design methodologies to handle increasingly complex SoC/IP designs within aggressive, market-driven schedules
•    Active participation in benchmarking of library, technology parameters, implementation strategy to enable design requirements of die size, power & speed.
•    Ensure quality adherence during all stages of the project life cycle. Drive thorough analysis of existing processes and recommend and implement the process improvements to ensure ‘Zero Defect’ chips
•    Enable technological innovations from day to day learning & project experiences
•    Actively work as part of team both locally & also with remote or multi-site teams

To Apply and for detailed JDs: Please Send your profiles at artibhatia@embeddedcareers.com and or get registered at embeddedcareers.com.

Arti Bhatia

Marketing Executive

Embedded Careers

Compiler Engineers(4-10 Yrs) Apply @ http://embeddedcareers.com/

BE|BTech|ME|MTech
c++, c, open source, fortran, compilers

Qualifications / Experience:

BS and 10+ years, MS and 8+ years or PhD and 4+ years in compiler development
Hands-on experience in complex compiler code generation and optimization in at least one major general purpose compiler for C/C++/Fortran a must
GCC compiler development (front, mid or backend development)
Experience with Open source contribution and interactions.
- Being a maintainer of parts of GCC code is big plus.
Excellent knowledge of micro-architectural features of modern microprocessors
Excellent programming/debugging skills at the Assembly level.
Very solid practical C/C++/Fortran experience.
Prior experience with performance analysis of programs, tuning and experience with analysis tools like profilers
Good interpersonal and communication (written and oral) skills
Experience with parallel programming domain (OpenMP, MPI, auto-parallelization etc) is a plus

Job Description: The Compiler Engineer is responsible for development and enhancement of high-performance production level C/C++/Fortran compilers. Compiler Engineers are expected to independently design and develop complex optimization passes. Compiler Engineers must work closely with performance analysts, Compiler QA and the Compiler support organization. As needed, Compiler Engineers also work on Performance Analysis of the compiler and produce analysis reports.

To Apply and for detailed JDs: Please Send your profiles at artibhatia@embeddedcareers.com and or get registered at embeddedcareers.com.

Arti Bhatia

Marketing Executive

Embedded Careers

DFT Engineers(3-8 Yrs) Apply @ http://embeddedcareers.com/

BE|ME|BTech|MTech

Mandatory Skills dft, soc, synthesis, sta, atpg, bist, scan
You will be a part of the Group which is a global leader in the design, manufacturing and marketing of microcontrollers (MCUs) and embedded processors in the automotive, consumer and industrial markets. These products include 8-, 16- and 32-bit MCUs, 16-bit digital signal controllers (DSCs) and 32-bit microprocessors, as well as wireless connectivity solutions.

Your main duties will be:

• Will be responsible for Designing and Implementing DFT techniques (Memory BIST/Scan /On-Chip Compression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin-muxing/Logic BIST) on complex SOCs to improve testability
• Test Modes implementation and verification, scan insertion including on-chip compression
• Implementing, integrating and verifying memory BIST and boundary scan
• Test vector (Stuck-at/At-speed/Path delay/SDD/IDDQ/Bridging fault) generation with high test coverage and simulations at gate level with timing (SDF)
• Closing working with Test Engineer and Product Engineer team to understand testability requirement for zero-defect
• Post-silicon bring-up support
• Basic understanding of complete SOC design and flow
• Cross functional teams interaction for issue resolution
• Participate in driving new DFT methodology and solutions to improve quality, reliability and in-system test and debug capability
• Mentoring new team members

To Apply and for detailed JDs: Please Send your profiles at artibhatia@embeddedcareers.com and or get registered at embeddedcareers.com.

Arti Bhatia

Marketing Executive

Embedded Careers

Opening for Physical Design Engineer Experience 5+ years Apply @ http://embeddedcareers.com/

BE|ME|BTech|MTech
Understanding Verilog HDL
Understanding Deep Submicron effects such as 90nm and below
Understanding OCV, DFM, DFY
Excellent Block level and Full-chip physical design skills
Self-motivated, leadership skills and experience working with global teams
Minimum 5 years of ASIC physical design experience
Back ground of ASIC Physical Design: Floor planning, Clock Tree Synthesis, P&R, extraction, EM/IR Drop Analysis, timing and Signal Integrity closure, physical verification, low power implementation etc
Hands on experience and expertise in Cadence, Synopsys, Magma or Mentor Physical Implementation Tools
Should have participated in a minimum of 3 fullchip tapeouts.

To Apply and for detailed JDs: Please Send your profiles at artibhatia@embeddedcareers.com and or get registered at embeddedcareers.com.

Arti Bhatia

Marketing Executive

Embedded Careers