BE|ME|BTech|MTech
| Mandatory Skills dft, soc, synthesis, sta, atpg, bist, scan You will be a part of the Group which is a global leader in the design, manufacturing and marketing of microcontrollers (MCUs) and embedded processors in the automotive, consumer and industrial markets. These products include 8-, 16- and 32-bit MCUs, 16-bit digital signal controllers (DSCs) and 32-bit microprocessors, as well as wireless connectivity solutions. Your main duties will be: • Will be responsible for Designing and Implementing DFT techniques (Memory BIST/Scan /On-Chip Compression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin-muxing/Logic BIST) on complex SOCs to improve testability • Test Modes implementation and verification, scan insertion including on-chip compression • Implementing, integrating and verifying memory BIST and boundary scan • Test vector (Stuck-at/At-speed/Path delay/SDD/IDDQ/Bridging fault) generation with high test coverage and simulations at gate level with timing (SDF) • Closing working with Test Engineer and Product Engineer team to understand testability requirement for zero-defect • Post-silicon bring-up support • Basic understanding of complete SOC design and flow • Cross functional teams interaction for issue resolution • Participate in driving new DFT methodology and solutions to improve quality, reliability and in-system test and debug capability • Mentoring new team members |
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Arti Bhatia
Marketing Executive
Embedded Careers
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