Mandatory Skills:The ideal candidate must have 5+ years of experience in Java/C++ SW development with strong OOP and SW design patterns knowledge.
FPGA Emulation Software Engineer
Location: San Diego, CA
We are currently seeking a Java/C++ software engineer to develop Java/C++ applications to automate FPGA emulation flow for FPGA platforms. As a member of FPGA emulation methodology team, you will work with FPGA emulation team to understand ASIC RTL codes and FPGA partition flow, work with board design team to understand board netlist and Verilog models, work with EDA venders to understand FPGA tool capabilities and Tcl command interface for integration.
• The candidate will develop Java/C++ application infrastructure from scratch to run in both GUI and batch modes cross over Unix/Linux and PC platforms.
• Work with HW engineers to develop SW algorithms and data structure for FPGA build and release automation.
• The SW infrastructure includes efficient parsing programs to parse big text files (10,000 files or 1GB size) to create XML based database.
• Text files include Verilog, EDIF and SDF (Standard Delay Format).
• To drive FPGA partition and synthesis, Tcl commands from EDA venders will be integrated.
• To configure and read FPGA status and errors in the FPGA emulation platforms Linux/PC PCIe driver and Ethernet socket will be integrated.
• Also version control function should be developed to keep RTL checkout and FPGA build release in track.
Skills / Experience:
• The ideal candidate must have 5+ years of experience in Java/C++ SW development with strong OOP and SW design patterns knowledge.
• Proficient in GUI and web app framework development such as Java Swing, JSF, J2EE, Servlet, Tomcat, MySQL, MVC frameworks.
• Experience with Unix/Linux backend and programming such as shell script and g++.
• Experience with version control such as ClearCase and CVS.
• Familiar with XML and HTML processing.
• Experience with performance tuning techniques and software unit test frameworks such as JUnit.
• Proficient in Java/C++ string process and data structure.
• The candidate should have solid problem analysis and solving capability.
Nice to have:
• Any experience with parser/compiler development based on open source Java/C++ parser such as ANTLR, Yacc, Lex.
• Knowledge of Verilog or VHDL language or EDIF netlist standard.
• Knowledge of ASIC/FPGA EDA design flow and tools.
• Knowledge of Java and C++ interface, Java and Tcl interface.
• Experience with Perl and Python.
• Experience with Java/C++ 2D graphics display and edit is a huge plus