Openings Input Output Layout & Verification, PCB Schematic Design Layout/Field Applications Engineers, Locations: USA, Malaysia & India. Exp: 2 -10 years. Mail @ artibhatia@embeddedcareers.com

Openings Input Output Layout & Verification, PCB Schematic Design Layout/Field Applications Engineers, Locations: USA, Malaysia & India. Exp: 2 -10 years. Mail @ artibhatia@embeddedcareers.com

Hi All.

Currently we are looking for

To Apply: Just logon to   http://embeddedcareers.com/. Or Send your profiles at artibhatia@embeddedcareers.com

1)     PCB Schematic Design Layout/Field Applications Engineer (Michigan, USA) Experience: 6-8 years

Domain (Automotives)

Mandatory Skills: Schematic Capture, PCB Layout, Circuit Simulation, Circuit Analysis

Desirable Skills: Cadence-based verification tools, Modeling, Mixed-signal verification

Job Description  

                Circuit Design for new LSI products and customer specific applications

·         

2)     Input Output Layout Engineer (Bangalore) Experience: 2-4 years

Mandatory Skills: IO library development-USB layout, HSTL layout, SSTL layout, GPIO layout, MFIO layout, LVDS layout

3)     Verification Engineer (Malaysia and Bangalore) Experience: 2-8years

Verilog/VHDL Language Proficiency

-     Hands-on experience in one of the Methodologies – OVM, VMM, AVM, UVM using SystemVerilog

-     Working Experience in one of the Protocols like USB, PCIe, DDR, SATA etc.

4) System Verilog / Specman / Vera Verification Engineer 
Job Location : Bangalore
Experience : 3 - 10 years
Job Description : BFMs Development, Test Case Development, Module and SOC level verification and ARM processor knowledge. Expertise in debugging tools is must. Good knowledge on code coverage, functional coverage tools, USB, PCIE and AHB/AXI.

5) SoC Level Physical Designer 
Job Location : Bangalore 
Experience : 3 - 8 years
Job Description : Place & Route (PnR), CTS, Floor Planning, Timing closure, Power Planning, IO planning, Synthesis, STA, MAGMA, ICC, Primetime, PTSI, Design Compiler, Apache, Calibre

6) DFT lead Engineer 
Exp: 3-8yrs
Location: Bangalore
Job Description : Strong knowledge of DFT including JTAG, MBIST, scan, on-chip scan compression, fault models, ATPG, and fault simulation and AC scan for at speed testing, Expertise in industry standard EDA tools for DFT such as DFTAdvisor, fastscan/TestKompress, TetraMax, Dft compiler

7) Analog Layout
Exp:2-9 years
Location: Banglore
Job description: Analog Mixed-Signal layout and verification for different complex analog circuits in 90nm node or lesser. Knowledge of half cell Tool Experience like Cadence Virtuso ,Vxl and Virtuoso, Schematic Composer, and verifications tools including Assura, Mentor/Synopsys Calibre /Hercules LVS, DRC, STarRC for extraction

8) IO layout
Exp:2-5 years
Location: Banglore
Job description: ASIC IO Library Development . Should have experience on tools like cadence, virtuoso layout editor .Good Knowledge on Verification Tools like ASSURA , Mentor, Hercules, lVS , HSPICE. Experience on any one of the design tools like USB LAYOUT ,HSTL LAYOUT ,SSTL LAYOUT ,GPIO LAYOUT ,MFIO LAYOUT ,LVDS LAYOUT .

To Apply: Just logon to   http://embeddedcareers.com/. Or Send your profiles at artibhatia@embeddedcareers.com

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Regards
Arti Bhatia 
Marketing Executive
Embedded Careers Email: artibhatia@embeddedcareers.com
LinkedIn: http://in.linkedin.com/in/artibhatia