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Sunday, June 3, 2012
Openings for DFT, Silicon Validation, Scan insertion, Design Engineers. Experience: Fresher to 8years. Location: Noida, Delhi NCR, Bangalore. Apply @ http://embeddedcareers.com/login.php
1) Engineers
with 5 to 7 yrs Exp. of Leading DFT team
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Led a DFT
team for at least two SOCs
- A hold over the complete flow i.e. scan, atpg, structures for delay test, coverage analysis, memory testing, netlist simulations and pattern delivery. - Ability to decide on the take decision on approaches - Ability to decide on the the schedule and effects on it due to different approaches. - Exposure to LBIST, mixed-signal testing and post-silcon bring up - Exposure to timing or synthesis and should be able to decide on the constraints for the same. |
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2) Engineers
with 3 to 5 yrs of Exp. in Scan insertion and DRC cleanup
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Scan
insertion and DRC cleanup
- Pattern generation for Stuck-At, delay test, iddq, path delay and fault grading. - Memory testing. Should also know the algorithms. Should also have knowledge about diagnostics. - JTAG or P1500 or other interface mechanism |
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- Compression tools is highly desirable - LBIST, mixed-signal testing, logic equivalence - Writing testbenches and should be capable of writing RTL code for DFT blocks as and when required. - Bridge fault detection is desirable - ATE experience is an added advantage |
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3) Silicon
Validation of Analog IP in SOC Exp: 4 to 8 yrs
|
VLSI
Testing - Post Silicon Validation of 22nm, 32nm, 45nm, 65nm and 90nm Analog
IPs
- Programming Languages: LABVIEW, C, C++, Assembly - Candidate should be able to setup LabVIEW based automation for Post Silicon Validation - Signal Integrity Analysis using Agilent-ADS and/ or Cadence - Allegro PCB designer - Candidate should have defined, developed and executed Test Plans for Analog Electrical Characterization of advanced
CMOS
I/O’s, Compensation blocks, DDR, BIDIRS, LVDS, PLL, Power Management Block,
LDO, ADC, etc.
- Perform Analog electrical characterization, Signal measurements with the ATE - Familiarity with High BW Oscilloscope, Pattern & Pulse Generator, Time Domain Reflectometry, Eye Analysis
4) Design
Engineers Exp: 2-5 years (System Verilog, Vera, Specman, E, VMM, OVM,
UVM)
Worked on
SoC level testbench and verification environment
Testbench
architecture, coding and good understanding of design issues in RTL
Testbench
generation, testvector creation, simulations, gate level simulations
Hands on
with System Verilog and Assertion based verification methodology
Atleast
2years of experience on HVL (System Verilog, Vera, Specman, E, VMM, OVM, UVM)
Should be
able to work independently and able to guide others
5) Design
Manager : ExP: 8 yrs
Worked on
SoC level testbench and verification environment
Testbench
architecture, coding and good understanding of design issues in RTL
Testbench
generation, testvector creation, simulations, gate level simulations
Hands on
with System Verilog and Assertion based verification methodology
Atleast
4years of experience on HVL (System Verilog, Vera, Specman, E, VMM, OVM, UVM)
Should be
able to work independently and able to guide other team members
Problem
solving capabilities with leadership qualities
Should have
managed a team of 10 or more engineers
6) Career
opportunity as core Design Engineer for Electronics & Communication
Engineering B.E/B.Tech from IIT/NIT/REC & other Premier colleges ,
M.tech-(IIT/IISC) 2012 pass outs with a min CGPA of 8 or 70%
To Apply
and for detailed JDs:Please send your profiles at artibhatia@embeddedcareers.comand
or get registered at embeddedcareers.com.
ArtiBhatia Marketing Executive Embedded Careers http://embeddedcareers.com http://embeddedcareers.blogspot.com/. http://twitter.com/#!/CareersAtEC https://www.facebook.com/embeddedcareers |
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