New Jobs @ http://www.embeddedcareers.com/

Hiring Asic Design, Embedded, and Firmware Engineers. Experience: 1 -10 years. Locations: Bangalore, Noida, Delhi NCR, Chennai, Hyderabad. Apply @ http://embeddedcareers.com/login.php

Hiring Asic Design, Embedded, and Firmware Engineers. Experience: 1 -10 years. Locations: Bangalore, Noida, Delhi NCR, Chennai, Hyderabad. Apply @ http://embeddedcareers.com/login.php

EmbeddedCareers.com has been looking for Asic Design, Embedded and Firmware engineers for some great openings with us. You can apply to these jobs @ http://embeddedcareers.com/login.php or send profiles at artibhatia@embeddedcareers.com.

Embedded Engineers (2-8 years): With good knowledge of C, C++, on Linux Platform. Skills: I2C, SPI, UART, USB, device Driver, BSP development. Board Bring up.

Device Driver, BSP development. Very Good C Programming, Assembly Language Programming.

Apply @ http://embeddedcareers.com/login.php

Good Understanding of CPU Architecture ARM, MIPS and PowerPC Hardware interfaces: Nand/NOR Flash, DDR SDRAM, PCI (variants), Ethernet MAC/PHY Protocols : I2C, SPI, UART, USB, device Driver, BSP development.

Board Bring up. Boot loader Porting/development. Hardware Diagnostics Development. Linux Porting, Linux Kernel and microcontroller Concepts. Customizing kernel + Porting + developing applications Linux Device Driver Development (Character devices) Good Concepts of Network Drivers File systems concepts.

ASIC Design Engineers (1-10 years): Multiple requirements across domain and all levels of Expertise.

Hard Macro, Block level implementation,3 yrs in PD implementation, Talus or ICC or PTSI. Take metrics from designers and find a block and placement of PTSI Target companies—All semiconductor companies, Freescale, ST Micro, AMD

TOP level CTS routing resource//knowing basics of CTS//4yrs//Olympus tool(1 to 2yrs) or TALUS or ICC-not a preference// Data base from main resource and to multiple triages//verification, physical verification Mentor graphics AE’s, Magma

Encounter/top level activity with Scripting experience, manual editing//specific tool-first encounter, special DB commands//Engineer who work on floor plan

Exposure to LBIST, mixed-signal testing and post-silcon bring up, LBIST, mixed-signal testing and post-silcon bring up

Scan insertion and DRC cleanup, JTAG or P1500,   Pattern generation for Stuck-At, delay test, iddq, path delay and fault grading. Writing testbenches and should be capable of writing RTL code for DFT blocks as and when required. 

HVL (System Verilog, Vera, Specman, E, VMM, OVM, UVM), Worked on protocols like AMBA AHB/AXI, MIPI, PCI Express, SATA, USB

Mandatory Skills:		(System Verilog, Vera, Specman, E, VMM, OVM, UVM) Should be able to work independently and able to guide others
Desirable Skills		Testbench generation, testvector creation, simulations, gate level simulations
Job Description
Core Competencies:  Worked on SoC level testbench and verification environment Testbench architecture, coding and good understanding of design issues in RTL Testbench generation, testvector creation, simulations, gate level simulations Hands on with System Verilog and Assertion based verification methodology  Atleast 2years of experience on HVL (System Verilog, Vera, Specman, E, VMM, OVM, UVM) Should be able to work independently and able to guide others You can collect Detailed JDS  @  http://embeddedcareers.com/index.php or mail us at artibhatia@embeddedcareers.com Arti Bhatia                                                                     Marketing Executive Embedded Careers http://embeddedcareers.com  http://embeddedcareers.blogspot.com/. http://twitter.com/#!/CareersAtEC  https://www.facebook.com/embeddedcareers

Openings for DFT, Silicon Validation, Scan insertion, Design Engineers. Experience: Fresher to 8years. Location: Noida, Delhi NCR, Bangalore. Apply @ http://embeddedcareers.com/login.php

1) Engineers with 5 to 7 yrs Exp. of Leading DFT team

Led a DFT team for at least two SOCs -    A hold over the complete flow i.e. scan, atpg, structures for delay test,      coverage analysis, memory testing, netlist simulations and pattern delivery. -    Ability to decide on the take decision on approaches -    Ability to decide on the the schedule and effects on it due to different approaches. -    Exposure to LBIST, mixed-signal testing and post-silcon bring up -    Exposure to timing or synthesis and should be able to decide on the constraints for the same.

2) Engineers with 3 to 5 yrs of Exp. in Scan insertion and DRC cleanup

Scan insertion and DRC cleanup -    Pattern generation for Stuck-At, delay test, iddq, path delay and fault grading. -    Memory testing. Should also know the algorithms. Should also have knowledge about diagnostics. -    JTAG or P1500 or other interface mechanism
-    Compression tools is highly desirable -    LBIST, mixed-signal testing, logic equivalence -    Writing testbenches and should be capable of writing RTL code for DFT blocks as and when required. -    Bridge fault detection is desirable -    ATE experience is an added advantage

3) Silicon Validation of Analog IP in SOC Exp: 4 to 8 yrs

VLSI Testing - Post Silicon Validation of 22nm, 32nm, 45nm, 65nm and 90nm Analog IPs -    Programming Languages: LABVIEW, C, C++, Assembly -    Candidate should be able to setup LabVIEW based automation for Post Silicon Validation -    Signal Integrity Analysis using Agilent-ADS and/ or Cadence - Allegro PCB designer -    Candidate should have defined, developed and executed Test Plans for Analog Electrical Characterization of advanced   CMOS I/O’s, Compensation blocks, DDR, BIDIRS, LVDS, PLL, Power Management Block, LDO, ADC, etc. -    Perform Analog electrical characterization, Signal measurements with the ATE -    Familiarity with High BW Oscilloscope, Pattern & Pulse Generator, Time Domain Reflectometry, Eye Analysis 4) Design Engineers Exp: 2-5 years (System Verilog, Vera, Specman, E, VMM, OVM, UVM)  Worked on SoC level testbench and verification environment Testbench architecture, coding and good understanding of design issues in RTL Testbench generation, testvector creation, simulations, gate level simulations Hands on with System Verilog and Assertion based verification methodology  Atleast 2years of experience on HVL (System Verilog, Vera, Specman, E, VMM, OVM, UVM) Should be able to work independently and able to guide others 5) Design Manager : ExP: 8 yrs Worked on SoC level testbench and verification environment Testbench architecture, coding and good understanding of design issues in RTL Testbench generation, testvector creation, simulations, gate level simulations Hands on with System Verilog and Assertion based verification methodology  Atleast 4years of experience on HVL (System Verilog, Vera, Specman, E, VMM, OVM, UVM) Should be able to work independently and able to guide other team members Problem solving capabilities with leadership qualities Should have managed a team of 10 or more engineers 6) Career opportunity as core Design Engineer for Electronics & Communication Engineering B.E/B.Tech from IIT/NIT/REC & other Premier colleges , M.tech-(IIT/IISC) 2012 pass outs with a min CGPA of 8 or 70% To Apply and for detailed JDs:Please send your profiles at artibhatia@embeddedcareers.comand or get registered at embeddedcareers.com. ArtiBhatia Marketing Executive Embedded Careers http://embeddedcareers.com http://embeddedcareers.blogspot.com/. http://twitter.com/#!/CareersAtEC https://www.facebook.com/embeddedcareers