Role | Project Trainee |
Eligibility | Preferably 1+ years of experience in VLSI/Digital Communications and B.E/B.Tech in E.CE./E.E.E/E.I.E or M.E./M.Tech in VLSI Design/Digital Communications/Digital Systems. Fresher’s also can apply. (If a fresher is considered and selected for Project Trainee position , an In-House 2 Months training will be provided.) |
Required Technical Skills | Strong Understanding of HDLs (VHDL/Verilog),VLSI Design, Digital Design, Basics of Electronics, Synthesis and FPGA Prototyping Knowledge |
Required Soft Skills | Team Player, Dedicating, Hard working, Flexible. |
Optional but Desired Skills | Working on Xilinx ISE, Teaching Experience is a plus. Preferably located in Hyderabad. |
Responsibilities | Developing Academic Projects for Vedic School of VLSI Design, representing Vedic in Seminars/Workshops, Mentoring the students. |
Role | Design Engineer |
Eligibility | Preferably 2-3 years of experience in VLSI/Digital Communications and M.E/M.Tech in VLSI Design/Digital Communications/Digital Systems. |
Required Technical Skills | Strong Designing, Debugging and Analyzing experience. Excellent knowledge of HDLs (VHDL/Verilog) with Hardware Orientation,VLSI Design, Digital Design, Basics of Electronics, Synthesis and FPGA Prototyping Knowledge. |
Required Soft Skills | Team Player, Dedicating, Hard working, Flexible. Should be able to work independently and self-motivate. |
Optional but Desired Skills | Leading Experience, Knowledge on Verification is Plus. Working on Xilinx ISE, Teaching Experience is an added advantage. Preferably located in Hyderabad. |
Responsibilities | Leading the designing team in front and closely working with tech directors to meet the designing and development goals. Responsible for designing the projects and deliver the projects in time. Should be well versed with designing and debugging. |
Arti Bhatia
Marketing Executive
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