- Must have prior full-chip DFT leadership experience handling large complex ASIC/SoC and should have handled at least one SoC tapeout.
- Should have hands-on experience with scan synthesis, scan DRC fixing, MBIST, LBIST, JTAG (IEEE 1149.1), On-chip scan compression techniques.
- Block level and Chip level ATPG, fault coverage improvements (aiming > 99% coverage) and simulation with timing, At-speed testing, transition and path delay ATPG.
- Excellent debugging skills " scan failures/blockage, DFT DRC failures, timing (setup/hold) failures for scan paths, signature analysis.
- Formal verification of DFT inserted netlists.
- Expertise in industry standard EDA tools for test such as DFT Advisor, Fastscan/TestKompress, TetraMax, DFT compiler
- Clear understanding and command over all aspects of physical design
- Worked on all aspects of physical design including synthesis, floorplanning, place and route, clock tree synthesis, IP integration,extraction, timing closure, power and signal integrity analysis,physical verification, DFM, and tapeout
- Expertise in Synopsys IC Compiler / Magma Talus / Cadence
- SoC Encounter
- Good Debugging skills
- Should have worked on SOC level verification on at least one project with constrained random methodology (eRM / VMM / OVM). Proficiency in one or more HVL’s - System Verilog, C++, Vera, e, System C, Test Builder - is a must.
- Strong domain knowledge on one or more of PCIe, USB, Ethernet, ARM, AHB / AXI, AMBA, PHY Layer is a must
- Must be expert in building a verification environment with any of the above methodology, writing and debugging test cases.
- Should be able to enhance the Verification Coverage, Code coverage & Functional Coverage.
- Working knowledge of any one scripting language like Perl, Python, Unix Make, Unix Shell Scripts etc. is a must.
To Apply: Please Send your profiles at arti.bhatia@embeddedcareers.com and or get registered at embeddedcareers.com.
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